PURPOSE: To shorten a processing time for a DMA data transfer by providing not only a single mode but also a page mode for reading out and writing plural data on a DRAM control circuit.

CONSTITUTION: In a DRAM (dynamic random access memory) control circuit 18, a temporary storage memory 18a for storing temporarily data of plural words read out or written simultaneously to and from a DRAM 17 is provided. Accordingly, with respect to the DRAM control circuit 18, not only a single mode but also a page mode for reading out and writing continuously plural data can be selected. In such a way, in accordance with necessity, the best operation mode can be selected, an interposed precharge time can be decreased, and the processing time for a DMA (direct memory access) data can be shortened.