PURPOSE: To guarantee the accurate execution of direct memory access (DMA) transfer operation setting up a high speed memory in a shared memory space as a transferred destination or a transferring source when a part of the memory space for the high speed memory and a low speed memory is shared.

CONSTITUTION: A central processing unit(CPU) 1 is provided with the high speed memory 1c in order to attain rapid processing and the memory space of the memory 1c is allocated as a partial memory space in the memory space of low speed memories 30b, 31b to guarantee the continuity of the memory space. In the case of starting the high speed memory 1c by a DMA controller at the time of DMA transfer in which the transferred destination/transferring source is the memory 1c, only the memory 1c is started by respective memory control circuits 1b, 30a, 31a and the start of the low speed memories 30b, 31b having the same memory space as that allocated to the memory 1c is suppressed.