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Patent Searching and Data


Title:
DOT MATRIX SYSTEM DISPLAY UNIT
Document Type and Number:
Japanese Patent JPS6267479
Kind Code:
A
Abstract:

PURPOSE: To enable selection at a high quality, by incorporating a decision circuit capable of varying a decision level by an external signal to permit the detection of difference and variations in the driving capacity of a transistor according to the results of responding to a plurality of decision levels.

CONSTITUTION: A reference level for deciding on the quality of a circuit at a pixel section is applied to a set terminal 12 of a decision circuit 4 from an external terminal Vs and a test operation is started. In the operation, an input control transistor Trin, a train selection transistor Tr4 and a writing transistor Tr1 are closed and a signal is inputted from a terminal Vv to be stored into a storage capacitance Cv. The voltage level at an output terminal T' where the stored signal is read out is compared with the reference level by the decision circuit to decide on the driving capacity of a corresponding pixel. Upon the completion of testing over the entire surface, the reference level is altered several times as required and the same test is carried out. This enables the discrimination of variations in the driving capacity of a transistor at the pixel part.


Inventors:
YOSHIMURA KATAHIRO
Application Number:
JP20908485A
Publication Date:
March 27, 1987
Filing Date:
September 20, 1985
Export Citation:
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Assignee:
SHARP KK
International Classes:
G09G3/20; G09G3/36; G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
JPS5799688A1982-06-21
JPS5738498A1982-03-03
Attorney, Agent or Firm:
Nishida Arata