DOUBLE DATA RATE SERIAL ENCODER

Title:

DOUBLE DATA RATE SERIAL ENCODER

Document Type and Number:

Japanese Patent JP2010259079

Kind Code:

A

Abstract:

To provide a glitch-less output during input transitions, in a double data rate serial encoder for an MDDI.

The serial encoder comprises latches to receive input parallel data, an enabler to enable the latches to input data while coupling latch outputs to a plurality of inputs of a multiplexer, and a counter to select one of the plurality of inputs of the multiplexer. The counter provides a gray code input selection value to the multiplexer and provides the glitch-less output during multiplexer selection input transitions.

More Like This:

WO/2012/134652	SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE
WO/2000/025431	SERIAL-TO-PARALLEL/PARALLEL-TO-SERIAL CONVERSION ENGINE
JP3990570	Clock data recovery circuit coupled to programmable logic device circuit

Inventors:

STEELE BRIAN
WILEY GEORGE A
MUSFELDT CURTIS

Application Number:

JP2010127069A

Publication Date:

November 11, 2010

Filing Date:

June 02, 2010

Export Citation:

Click for automatic bibliography generation Help

Assignee:

QUALCOMM INC

International Classes:

H03M9/00; H04L13/10

Domestic Patent References:

JPH11249987A	1999-09-17
JPH09307457A	1997-11-28
JP2001320280A	2001-11-16
JPS648731A	1989-01-12
JP2000236260A	2000-08-29
JP2000324135A	2000-11-24
JPH07115352A	1995-05-02
JP2002281007A	2002-09-27
JP2004531916A	2004-10-14

Foreign References:

US6594304B2

2003-07-15

Attorney, Agent or Firm:

Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen

Previous Patent: INFORMATION PROCESSING APPARATUS, AND INITIALIZING METHOD FORF SETTING ITEM OF THE SAME

Next Patent: BROADCAST DATA PROCESSING APPARATUS AND BROADCAST DATA PROCESSING METHOD