DOUBLE DATA RATE SYNCHRONOUS DRAM INTEGRATED CIRCUIT DEVICE

Title:

DOUBLE DATA RATE SYNCHRONOUS DRAM INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JP3663082

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a double data rate synchronous DRAM integrated circuit device which can be tested by a low speed test device.
SOLUTION: Single data rate mode signals CL1, BL1 are activated, and a double data rate synchronous DRAM integrated circuit device is operated with a single data rate mode. The device has a first buffer 111, a pulse generator 121, a first logic circuit 131, a second buffer 151, a second logic circuit 141, a first control section 161, and a second control section 171, when the single data rate mode signals CL1, BL1 are made logic-high, an internal data strobe signal PDS is generated, also a second internal masking signal DMS is made logic-high, a second data Did S is masked, and writing the second data Did S is prohibited.

Inventors:

Ramon
Lee Jun-pei
Lee

Application Number:

JP19669699A

Publication Date:

June 22, 2005

Filing Date:

July 09, 1999

Export Citation:

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Assignee:

Samsung Electronics Co.,Ltd.

International Classes:

G11C11/407; G11C7/10; G11C11/401; G11C29/00; G11C29/12; G11C29/48; (IPC1-7): G11C29/00; G11C11/401; G11C11/407

Domestic Patent References:

JP7078498A
JP7140207A
JP7078495A
JP10172282A
JP7262769A

Attorney, Agent or Firm:

Makoto Hagiwara

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