To make permit for the output pulse setting-operation period by forming the plural optional number of output clocks having the high resolution and high frequency by using a same basic clock and also to produce a pulse having the length of a period shorter than a basic clock period.

In the driving clock producing device, 1st, 2nd and 3rd frequency dividing delay circuits 2a, 2b and 2c, and 1st, 2nd and 3rd selecting circuits 3a, 3b and 3c are constituted so as independently operative with the time difference, and a delay pulses group outputted from each frequency dividing delay circuit is selected by pulse selecting data 1, 2 and 3 supplied from a pulse selection control circuit 5, and the output pulse is produced by a synthetic circuit 4 from the output of each selecting circuit. In three frequency dividing delay circuits, the time of the basic clock period is deviated and the pulse producing operation is carried out by start signals (S1, S2 and S3) of a start control circuit 6. The delay pulses group which is the output of each frequency dividing delay circuit, is equivalent to that a time base is filled up by the pulses having delay time intervals (T), and the production of an output pulse train up to the basic clock period can be optionally carried out.