Title:
ドループ・フリーな疑似連続再構成フィルタ・インターフェース
Document Type and Number:
Japanese Patent JP3553545
Kind Code:
B2
Abstract:
A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter. An input sampling circuit is operative to store a sample of the output signal from the digital to analog converter. An input pulse generating switch that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter. An amplifier receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter.
Inventors:
Shen, Samuel W
Conroy, Colmac S
Conroy, Colmac S
Application Number:
JP2001500439A
Publication Date:
August 11, 2004
Filing Date:
May 24, 2000
Export Citation:
Assignee:
LSI LOGIC CORPORATION
International Classes:
H03M1/66; H03H19/00; H03M1/06; H04B3/04; H04J11/00; H03M1/08; (IPC1-7): H04J11/00; H03H19/00; H03M1/66; H04B3/04
Domestic Patent References:
| JP6350403A |
Foreign References:
| US4968989 |
Attorney, Agent or Firm:
Kazuo Shamoto
Shosuke Imai
Tadashi Masui
Yasushi Kobayashi
Hiroyuki Tomita
Otsuka Naruhiko
Shosuke Imai
Tadashi Masui
Yasushi Kobayashi
Hiroyuki Tomita
Otsuka Naruhiko