To provide a memory cell layout of a dual port semiconductor memory device including a PMOS scan transistor.
A dual port semiconductor memory device comprises two PMOS load transistors, two NMOS pull-down transistors, two NMOS pass transistors, and one PMOS scan transistor, wherein the scan transistor being the PMOS transistor, thereby improving a noise margin of the dual port semiconductor memory device. The above seven transistors are arranged in two N-wells and two P-wells, wherein the N-wells and P-wells are alternately arranged in a row, and as a result, the length of the memory cell in a minor axis direction is relatively short. According to the memory cell layout, by arranging a pair of bit lines in a direction parallel to the well boundary surface, that is, in a minor axis direction, the lengths of the bit lines are shortened, and further, by arranging a conductive line having a fixed potential between the bit line and the complementary bit line, interference phenomenon caused between the pair of the bit lines can be prevented.
KIN HEIZEN
LEE JOON HUNG
| JPH10178110A | 1998-06-30 | |||
| JPH05265421A | 1993-10-15 |
| US20020174298A1 | 2002-11-21 |
Atsushi Nogami
Yasuo Nara
Etsuko Saito
Katsuyuki Utani
Toshifumi Fujii
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