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Title:
DUAL SYSTEM FOR CLOCK GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH02134022
Kind Code:
A
Abstract:

PURPOSE: To avoid system-down without switching a clock oscillation source by devising the system such that the normality of other clock signal supplied to a dual circuit device is kept even if one oscillation source for a clock generating circuit provided with the two oscillation sources is faulty.

CONSTITUTION: The oscillated output of a crystal oscillator 10 is fed to one device 18-1 in the dual devices as a 1st clock signal (a) and the oscillated output of a voltage controlled oscillator 16 is fed to the other device 18-2 as a 2nd clock signal (b). Even if one clock oscillation source is faulty, since the two clock signals (a), (b) are completely synchronized till the occurrence of the fault, then no phase shift of the clock takes place even after the clock signal is stopped, the operation of the device receiving the normal clock signal is continued. Thus, no switching of the clock oscillation sources is required to avoid the system stop.


Inventors:
KUDO TETSUO
Application Number:
JP28800388A
Publication Date:
May 23, 1990
Filing Date:
November 15, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/18; G06F1/04; H03L7/00; (IPC1-7): G06F1/04; G06F11/18; H03L7/00
Domestic Patent References:
JPS56169435A1981-12-26
Attorney, Agent or Firm:
Susumu Takeuchi (1 person outside)



 
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