To facilitate a correction of wiring, to eliminate reexecution of CTS, and to shorten TAT for verifying the timing by dispersively arranging dummy elements.

A dummy element adding process (S3, and S4) in a layout of a logic gate of an integrated circuit is characterized by dispersively arranging the dummy elements used for correcting logic by predetermining an insertion rate of the dummy elements to the number of respective cells of a net list including the dummy elements on the layout when requiring to correct the layout because of the occurrence of problems of the logic change and timing not converging.