Title:
DUPLEX PROCESSOR
Document Type and Number:
Japanese Patent JPH04211841
Kind Code:
A
Abstract:
PURPOSE: To offer a device which does not stop duplex operation in the case of a transitory error.
CONSTITUTION: When the error is detected in data from a memory 12, the operation of a CPU 11 is stopped temporarily by a stoppage decision logic means 17, and retrial is executed by a bus control unit 16. If the error disappears by this retrial, the CPU 11 restarts the operation, and if the error is not restored, the bus control unit 16 disconnects a system in which the error occurred.
Inventors:
HAYASHI TAKAO
Application Number:
JP5365991A
Publication Date:
August 03, 1992
Filing Date:
February 27, 1991
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F11/14; G06F11/18; G06F15/16; G06F15/177; (IPC1-7): G06F11/14; G06F11/18; G06F15/16
Attorney, Agent or Firm:
Masaki Yamakawa