LOAD/MIGRATION AND DUPLICATION INSTRUCTION RELATIVE TO PROCESSOR

Title:

LOAD/MIGRATION AND DUPLICATION INSTRUCTION RELATIVE TO PROCESSOR

Document Type and Number:

Japanese Patent JP2014089730

Kind Code:

A

Abstract:

To provide a method for loading/migrating a part of bits of a source in a processor to a destination register.

One and a plurality of migration/duplication instructions order a processor to store a plurality of bits from a non-continuous position group of a single source operand in a non-continuous destination position group of a destination register and to duplicate a bit from each of the non-continuous position group of the single source operand to another destination position group in the destination register. The non-continuous position group of the single source operand to which duplication is performed is fixed relative to the single migration/duplication instruction not explicitly defined by the single migration/duplication instruction.

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Inventors:

ROUSSEL PATRICE

Application Number:

JP2013257903A

Publication Date:

May 15, 2014

Filing Date:

December 13, 2013

Export Citation:

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Assignee:

INTEL CORP

International Classes:

G06F1/00; G06F9/315; G06F9/312; G06F9/38

Domestic Patent References:

JPH0916397A	1997-01-17
JPH10240528A	1998-09-11
JPH08314898A	1996-11-29
JPS61294550A	1986-12-25
JPH0916397A	1997-01-17
JPH10240528A	1998-09-11

Foreign References:

US6115812A	2000-09-05
US6115812A	2000-09-05

Other References:

JPN6009041750; 池井満: "ＩＡ-６４プロセッサ基本講座" , 20000825, ｐ．１５０-１５１，１６０-１６１, 株式会社オーム社
JPN6009041750; 池井満: "ＩＡ-６４プロセッサ基本講座" , 20000825, ｐ．１５０-１５１，１６０-１６１, 株式会社オーム社

Attorney, Agent or Firm:

Tadashige Ito
Tadahiko Ito
Shinsuke Onuki

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