Title:
DUTY CORRECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3458782
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To execute demodulation with a low bit error rate through the use of a reproduction clock with high precision and a signal with a corrected waveform distortion by inverting a reception signal when the waveform distortion is detected and correcting the waveform.
SOLUTION: When the pulse width of the reception signal becomes larger than a setting value, a counter 3 is reset by a reset pulse outputted from an edge detecting circuit 2. A selector signal L is outputted from a waveform distortion detecting circuit 4 while the a counter output is between one to eight and a selector 5 selects the reception signal and outputs it. When the counter output becomes nine, the circuit 4 judges the waveform distortion and outputs the selector signal H. The selector 5 selects the inversion signal of the reception signal and outputs it. Thus, the H of the reception signal is forcibly made to be L so that the DUTY ratio of a correcting signal is improved. The DUTY ratio becomes nearly 50% in the correcting signal and, then, the reproduction clock with higher precision is generated.
Inventors:
Yasushi Sokabe
Fumio Ishizu
Fumio Ishizu
Application Number:
JP23342899A
Publication Date:
October 20, 2003
Filing Date:
August 20, 1999
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K5/04; H03M5/12; H04L25/49; (IPC1-7): H03K5/04; H03M5/12; H04L25/49
Domestic Patent References:
| JP11127142A |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)