Title:
DUTY CORRECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3478290
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a duty correction circuit with a low bit error rate by means of demodulation using signals whose waveform distortion is corrected.
SOLUTION: Waveform distortion is detected by observing waveforms and the distortion is corrected. Even when it is impossible to maintain a duty ratio of 50% of a received Manchester signal, the ratio of a corrected signal becomes nearly 50% by using this duty correction circuit, and a more accurate regeneration clock can be generated. Also by using a highly accurate generation clock and signals whose distortion is corrected, demodulation with a low bit error rate can be realized.
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Inventors:
Yasushi Sokabe
Fumio Ishizu
Fumio Ishizu
Application Number:
JP2002107680A
Publication Date:
December 15, 2003
Filing Date:
August 20, 1999
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K5/04; H03M5/12; H04L25/03; H04L25/49; (IPC1-7): H04L25/49; H03K5/04; H03M5/12; H04L25/03
Domestic Patent References:
| JP11127142A | ||||
| JP1188447A | ||||
| JP4290305A | ||||
| JP9139659A | ||||
| JP77918B2 |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)