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Title:
DUTY-CYCLE CONTROL APPARATUS
Document Type and Number:
Japanese Patent JPH06249922
Kind Code:
A
Abstract:

PURPOSE: To provide a duty-cycle control apparatus wherein an internal control clock in each functional block at the inside of an LSI chip can be controlled precisely and, consequently, the precise duty-cycle dependence of each functional block inside the LSI chip can be measured.

CONSTITUTION: An input-clock generation device 2 generates an input clock to an LSI chip 7. An internal-control-clock dutycycle detection device 5 detects the duty cycle of an internal control clock which is output to the outside from a monitoring pad 9 on the LSI chip 7. A duty-cycle correction device 6 controls the input-clock generation device 2 on the basis of an expected value from a clock-duty-cycle expected-value setting device 1 and on the basis of a detection result by the internal-control-clock duty-cycle detection device 5. Thereby, the duty cycle of the input clock is corrected.


Inventors:
KISHIDA TAKESHI
Application Number:
JP3572893A
Publication Date:
September 09, 1994
Filing Date:
February 24, 1993
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/28; G05F1/08; G06F1/04; G01R31/3183; (IPC1-7): G01R31/28; G05F1/08; G06F1/04
Attorney, Agent or Firm:
Nakajima Shiro