To inhibit another processing in the period from a fast forwarding end instruction up to the end of an actual fast forwarding period by adding a fast forwarding period identification code after a prescribed code included in each frame image data.
Coded dynamic image data transferred from communication media is serially inputted to a shift register 24, and a comparator circuit 26 compares a parallel output of the register 24 with a picture start code outputted in parallel from a picture start code storage circuit 25. When the picture start code is detected, a selector 29 is controlled so as to insert a fast forwarding period identification code outputted by a fast forwarding period identification code storage circuit 27 after the picture start code in coded dynamic image data outputted in series from the register 24. The circuit 27 outputs '1' as the fast forwarding period identification code in a period since a fast forwarding instruction is issued until an end instruction is issued and outputs '0' in the other period.
ISHIZUKA MASANORI
KONO TADAMI
Next Patent: DIGITAL TV BROADCASTING TRANSMITTER AND ITS RECEIVER