To reduce the occupancy area of a dynamic logic circuit while lightening the load of the circuit or wiring design and securing operation reliability.

This circuit has a precharging transistor Npc, which is connected between an output node ND and a source voltage supply line and accumulates electric charges in an output node ND by turning on for a precharging period, wherein a clock signal CLK has a 1st potential according to the clock signal CLK and a logic circuit 2 which is connected between the output node ND and an input terminal for the clock signal CLK and determines the logic state from an input signal IN received in the precharging period and draws accumulated electric charges of the output node ND out of the input terminal for the clock signal CLK by the potential difference between the output node potential and a 2nd potential in an evaluation period, wherein the clock signal CLK has the 2nd potential when a current path is generated inside according to the determined logic state to generate an output signal OUT.