PURPOSE: To prevent malfunction due to parasitic capacitance by arranging closely a logic gate set to a high voltage level and a logic gate set to a low voltage level as an initial potential during precharge period.

CONSTITUTION: A logic gate including an OR and an AND is incorporated simultaneously in the same function logic circuit group and a logic gate set to a high voltage level and a logic gate set to a low voltage level as an initial potential during precharge period are arranged close to each other. Thus, the dynamic logic circuit array by a high density circuit pattern is realized without being affected by a voltage drop due to parasitic capacitance sets C01, C12 in which output points are arranged physically, adjacently or alternately. Thus, malfunction of the transition of the adjacent dynamic gate for a holding period due to the effect of the sets of parasitic capacitance C01, C12 is prevented and the logic gate output points are coupled mutually by a capacitive element to correct the logic level positively by the bootstrap effect.