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Title:
DYNAMIC TYPE RAM AND THE PLATE VOLTAGE SETTING METHOD AND INFORMATION SYSTEM
Document Type and Number:
Japanese Patent JPH06243678
Kind Code:
A
Abstract:

PURPOSE: To highly efficiently use the storage operation of a memory cell by using a high dielectric film for an information storage capacitor and using a difference generating in leak current in the polarity of impression voltage.

CONSTITUTION: A memory cell is connected with one of complementary bit lines BLT and BLB at the intersected points with a word line. In an information capacitor, a high dielectric film is used to have small occupancy area and large capacity. In this case, a difference is generated between the high level writing voltage +VBLmax and low level writing voltage -VBLmax from the bit line side at the time of same leak current. Then, the both of them are measured and plate voltage VPL is set. Namely, the voltage VPL is determined so that addition voltage may be a bit line high level VH (VCC) in the absolute value of the voltage. Normally, as the bit line high level VH is determined by power source voltage VCC, the addition voltage of the absolute value of voltage +VBLmax and -VBLmax is determined so as to be voltage VCC within the allowable value determined from a refresh synchronizing, etc., by leak current.


Inventors:
NAKAMURA MASAYUKI
MATSUMOTO TETSUO
OSHIMA KAZUYOSHI
Application Number:
JP5511193A
Publication Date:
September 02, 1994
Filing Date:
February 19, 1993
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/404; G11C11/407; G11C11/4074; (IPC1-7): G11C11/404
Attorney, Agent or Firm:
Tokuwaka Mitsumasa



 
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