PURPOSE: To detect a defect existing spot with being limited in each block by providing a distributing means to give a driving voltage to one of memory arrays in response to a block selecting signal from an external part.
CONSTITUTION: Memory arrays 1W4 are respectively connected to a word line. A distributing circuit 80 is provided between a word line boost circuit 10 and a raw decoder. The distributing circuit 80 responds to low level control signals S, BS0 and BS1 from a test signal generating circuit 90 and selectively gives a boosted word line WDB to respective raw decoders 1aW4a. Namely, the block selecting signals BS0 and BS4 are decoded by a decoder 81, which includes an AND gate and an inverter, and a switching circuit 82 includes a NOR gate, an inverter an NchFET and a power source resistor. Then, a decode output and the switching signal S of a low level are received and the word line driving signal WDB is selectively transmitted to the memory array. The signal WDB of the memory array of non-selection is a grounding level. Such a DRAM device normally opens the reserve pad of the distributing circuit 80 and the S is keep at a high level. Thus, the defect existing spot can be discriminated for the unit of block.
KUMANOTANI MASAKI
KONISHI YASUHIRO
YAMAZAKI HIROYUKI
| JPS61199297A | 1986-09-03 | |||
| JPS581890A | 1983-01-07 |