Title:
メモリの動的電圧調整
Document Type and Number:
Japanese Patent JP5462160
Kind Code:
B2
Abstract:
A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.
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Inventors:
Kuresh, Kadia A.
Dava, Susama
Jeu, Thomas
Dava, Susama
Jeu, Thomas
Application Number:
JP2010517037A
Publication Date:
April 02, 2014
Filing Date:
May 28, 2008
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G11C29/50; G01R31/28; G11C11/413
Domestic Patent References:
| JP2009076169A | ||||
| JP2003007094A | ||||
| JP11213667A | ||||
| JP9153290A | ||||
| JP2008181648A | ||||
| JP2004005777A | ||||
| JP2006114078A | ||||
| JP2009176340A |
Attorney, Agent or Firm:
Yasushi Kobayashi
Shigeo Takeuchi
Osamu Yamamoto
Shigeo Takeuchi
Osamu Yamamoto