Title:
EMI低減装置および方法
Document Type and Number:
Japanese Patent JP4027466
Kind Code:
B2
Abstract:
In a computer or other digital system a clock or other synchronous signal (12) is routed from a source (16) to a destination (18) as a double side band suppressed carrier (DSB-SC) signal (14). The clock or other synchronous signal is amplitude modulated at the source using a broadband low frequency envelope signal (20). The modulated signal is the DSB-SC signal, which then is routed over PC board traces (15) to the destination. At the destination, the DSB-SC signal is demodulated to achieve the clock or other synchronous signal (60). The envelope signal (20,20') is separately generated from a common key (72) at both the source and destination, is routed to bother the source to the destination, or is routed from the source to the destination.
Inventors:
David W Arnett
Application Number:
JP20651197A
Publication Date:
December 26, 2007
Filing Date:
July 31, 1997
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F1/04; G06F1/10; H03D1/24; H04B1/04; H04B15/04; H04L7/00; H04L27/04
Domestic Patent References:
| JP4190409A | ||||
| JP7505267A | ||||
| JP61024321A | ||||
| JP3265014A | ||||
| JP6177796A |
Attorney, Agent or Firm:
Shoichi Okuyama
Arihara Koichi
Matsushima Tetsuo
Arihara Koichi
Matsushima Tetsuo