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Patent Searching and Data


Title:
ECHO CANCELLING DEVICE
Document Type and Number:
Japanese Patent JPS59167131
Kind Code:
A
Abstract:

PURPOSE: To improve the echo cancelling capacity overall to improve the service quality by providing a detecting circuit which detects whether signals other than an echo signal are added to a receiving signal or not and using an estimated echo path of a register instead of a current estimated echo path when they are detected.

CONSTITUTION: An estimated echo path delay circuit HSFT 404 is provided for attaining an estimated echo path (k-T'+1) of T'-number of samples ago and consists of a shift register to which an estimated echo path HI(K) from an EST 403 is inputted and has individual elements hi(k) (i=1∼N) shifted by T'-number of samples to output hi(k- T'+1). At a time other than a simultaneous call time, a switch 505 selects a terminal B by a signal from a control circuit 504, and HI(k+1) corrected by it is loaded to an H register 501 instead of HI(k). Consequently, an ordinary echo path estimating operation is performed at this time. When a simultaneous call is detected, the control circuit 504 instructs the switch 505 to select a terminal C, and an estimated echo path HI(K- T'-1) of T'-number of samples ago from the HSFT 404 is loaded to the H register 501, and thereafter, the control circuit 504 instructs the switch 505 to select a terminal A, and thus, a disturbed estimated echo path is eliminated to return to an estimated echo path before disturbance.


Inventors:
MINAMI SHIGENOBU
Application Number:
JP4073783A
Publication Date:
September 20, 1984
Filing Date:
March 14, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H04B7/015; H04B3/23; (IPC1-7): H04B7/015
Attorney, Agent or Firm:
Noriyuki Noriyuki