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Patent Searching and Data


Title:
ECHO ERASER
Document Type and Number:
Japanese Patent JPS5784633
Kind Code:
A
Abstract:

PURPOSE: To enable circuit integration with an arbitrary circuit scale suitable for the requirements on a communication system, low cost and high quality, by connecting echo erasing unit circuits of the same constitution in cascade.

CONSTITUTION: An input of an echo erasing unit circuit 42 at a terminal 3 is transmitted to an external transmission line 43 from a terminal 4, and inputted to a terminal 1 at transmission side via 2/4 wire converter and outputted from a terminal 2 after processing of subtraction. The device is provided with the final tap for a circuit corresponding to tapped delay line in the circuit 42, a convolutional integrating circuit for the determination of tap coefficient, a divider, a square adder and input/output terminals 14, 16, 27, 35∼37, 39∼41 to correct the amount of echo ek at the terminal 2 to the input at the terminal 3 through external connection between terminals to zero. Unit circuits 42, 42', 42" having the same constitution are connected in cascade, allowing to make echo erase having the amount of delay of a integer multiple.


Inventors:
TAKAHASHI KENZOU
SAKAMOTO TAKASHI
Application Number:
JP16011080A
Publication Date:
May 27, 1982
Filing Date:
November 15, 1980
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04B3/23; (IPC1-7): H04B3/23