Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP3206665
Kind Code:
B2
Abstract:
PURPOSE: To read fault information by permitting a control CPU to communicate with a sub-CPU through a conversation memory and requesting thread out from the sub-CPU when the control CPU of a processor to be read out the fault information occurs a serious fault.
CONSTITUTION: When there is the read request of the fault table 8 of a processor 2a from a console 1, the control CPU 6 of a processor 2n checks a fault management table 19 in a self processor. When the state of the processor 2a is the serious fault, the read request is registered to the conversation memory 16 of the self processor 2n and outputs it to the sub-CPU 14. It recognizes request registration and requests the reading of the fault table 8 to the processor 2a via a diagnostic bus 5. The processor 2a reads the fault table 8 by the sub- CPU 14 and makes a response to the sub-CPU 14 in the processor 2n through the diagnostic bus 5. The sub-CPU 14 of reception registers the request in the conversation memory 16, reads it and makes the response to the console 11.
Inventors:
Akio Toda
Application Number:
JP18956491A
Publication Date:
September 10, 2001
Filing Date:
July 04, 1991
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06F15/16; G06F15/177; (IPC1-7): G06F15/177
Domestic Patent References:
| JP188677A | ||||
| JP3131956A |
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)
Previous Patent: A tray for packing boxes
Next Patent: PROTECTIVE CIRCUIT OF MOS SEMICONDUCTOR DEVICE OF ONE CONDUCTIVITY TYPE
Next Patent: PROTECTIVE CIRCUIT OF MOS SEMICONDUCTOR DEVICE OF ONE CONDUCTIVITY TYPE