Title:
電子機器の効率的なクロック較正
Document Type and Number:
Japanese Patent JP4994456
Kind Code:
B2
Abstract:
A representative measurement indicating a relative oscillation speed of a reference clock during a representative calibration period is ascertained. Multiple calibration periods are defined including first and second calibration periods. The first calibration period begins at a first start time, wherein a first time offset value is equal to a difference between the first start time and a transition point of the reference clock signal within the first calibration period. The second calibration period begins at a second start time, wherein a second time offset value is equal to a difference between the second start time and a transition point of the reference clock signal within the second calibration period. The first and second time offset values are different from one another. Measurements are generated by, for each one of the calibration periods, measuring the speed of the reference clock. The measurements are then averaged.
Inventors:
Hartsen, Jacobs
Application Number:
JP2009531799A
Publication Date:
August 08, 2012
Filing Date:
September 11, 2007
Export Citation:
Assignee:
Telefon Akti Bora Get Elm Ericson (Pubble)
International Classes:
H04W56/00; B65D39/12; H03L1/00; H03L7/00; H04W52/02
Domestic Patent References:
| JP2004282264A | ||||
| JP2003502980A |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Toshifumi Onuki