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Title:
EFFICIENT READ, WRITE METHOD FOR PIPELINE MEMORY
Document Type and Number:
Japanese Patent JP2009259253
Kind Code:
A
Abstract:

To provide methods and apparatus for efficiently writing data to and reading data from multi-state memory cells.

A memory system includes a first storage element, a data source, a first element, a second element, and a ripple clock. The data source outputs a plurality of bits to be stored in the first storage element, and the first element receives a first bit from the data source, and also clocks the first bit into the second buffering element. The first element then receives a second bit of the plurality of bits from the data source substantially while the first bit is being stored into the first element. The ripple clock enables access to the first element and the second element such that the first bit and the second bit may be pipelined.


Inventors:
GONGWER GEOFFREY S
Application Number:
JP2009120417A
Publication Date:
November 05, 2009
Filing Date:
May 18, 2009
Export Citation:
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Assignee:
SANDISK CORP
International Classes:
G06F12/00; G11C16/02; G11C7/10
Domestic Patent References:
JP2000149556A2000-05-30
JPH0896573A1996-04-12
JPH11162183A1999-06-18
JPH0489698A1992-03-23
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita



 
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