Title:
ELECTRIC FUSE CIRCUIT AND SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JP2009135329
Kind Code:
A
Abstract:
To provide an electric fuse circuit with reduced circuit scale.
The electric fuse circuit includes many cell circuits each having a first switch circuit and a fuse that are connected in series between a first terminal and a second terminal, a single node where many first terminals on many cell circuits are coupled in common, a single second switch circuit to be coupled between the single node and a single data output terminal, and a single third switch circuit to be coupled between the single node and a first supply voltage. The electric fuse circuit is configured to allow one of many first switch circuits on many cell circuits to be selectively conductive.
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Inventors:
ASHIZAWA TETSUO
MAKI YASUHIKO
UETAKE TOSHIYUKI
KODAMA TAKESHI
AKIYOSHI HIDEO
MAKI YASUHIKO
UETAKE TOSHIYUKI
KODAMA TAKESHI
AKIYOSHI HIDEO
Application Number:
JP2007311363A
Publication Date:
June 18, 2009
Filing Date:
November 30, 2007
Export Citation:
Assignee:
FUJITSU MICROELECTRONICS LTD
International Classes:
H01L21/82; G11C17/06; H01L27/10
Attorney, Agent or Firm:
Tadahiko Ito