Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3109456
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To always supply a constant current despite the variance of characteristic of a MOS transistor TR serving as a load by preparing a standard current source and a current mirror circuit having the value equal to the current value of the current source and making the current source use a saturation area of the MOS TR.
SOLUTION: An nMOS TR 1 applies a constant current V1 to a control terminal 12 to flow an approximately constant current (in) in a saturation area, applies the self-bias to the gate voltage of a pMOS TR 2 to flow the same current and is also biased by a pMOS TR 3 at the same voltage level. Therefore, the current value (ip) is supplied when the TR 3 operates in the saturation area. In the same way, a pMOS TR 4 flows an approximately constant current (ip) in the saturation area by applying the constant voltage V2 to a control terminal 13. Then the TR 4 applies the self-bias to the gate voltage of an nMOS TR 5 and is also biased by an nMOS TR 6 at the same voltage level.
Inventors:
Hiroshi Yamaguchi
Application Number:
JP19507097A
Publication Date:
November 13, 2000
Filing Date:
July 04, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L21/822; G05F3/26; H01L27/04; H03F1/30; H03K17/14; (IPC1-7): H03F1/30; H01L21/822; H01L27/04
Domestic Patent References:
| JP5974714A |
Attorney, Agent or Firm:
Asamichi Kato
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