To distribute a multi-phase clock up to each digital signal processing part, to which high-speed operation is requested, while properly keeping the phase relationships of clock signals when performing digital signal processing using the multi-phase clock.
A reference timing generating part 110 generates a reference timing signal J0, whose toggle frequency is lower than that of an entire high-speed signal processing part 140, and supplies it to a local timing reproducing part 120. The local timing reproducing part 120 generates a multi-phase timing signal J2 comprised of a plurality of clock signals, whose toggle frequency is lower than that of the entire high-speed signal processing part 140 and which become a reference of digital signal processing in the high-speed signal processing part 140, and supplies it to the high-speed signal processing part 140. The high-speed signal processing part 140 and the local timing reproducing part 120 are provided in one-to-one correspondence, thereby preventing the multi-phase timing signal J2 from being distributed from one local timing reproducing part 120 to a plurality of high-speed signal processing parts 140.
| WO/2005/050392 | GEOMETRIC REMAPPING WITH DELAY LINES |
| JPS566525 | 2-PHASE CLOCK PULSE GENERATING CIRCUIT |
| JPH08237142A | 1996-09-13 | |||
| JPH02296410A | 1990-12-07 | |||
| JPH06216705A | 1994-08-05 | |||
| JPH08316802A | 1996-11-29 | |||
| JP2007096903A | 2007-04-12 | |||
| JP2002158566A | 2002-05-31 | |||
| JP2001217695A | 2001-08-10 |
Masaaki Yoshii
Koichi Mori
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