Title:
電子部品装着位置補正方法および電子部品装着位置補正装置
Document Type and Number:
Japanese Patent JP5823174
Kind Code:
B2
Abstract:
The present invention relates to a solder paste mark setting method and solder paste mark setting device which make it possible to accurately determine the misalignment amount of the solder paste and to accurately correct the mounting position of an electronic component. The solder paste mark setting method consists of an imaging process in which an image is taken of areas G4, G5 which contain solder paste areas (on which solder paste is deposited) Ea1, Ea2, Eb-ed and non solder paste areas (on which solder is not deposited) of a master printed circuit board Bf0 on which solder paste has been deposited to specific positions on lands Da1, Da2, Db-Dd of the circuit pattern Ca1, Ca2, Cb-Cd and in which image g4 of areas G4 and G5 is acquired; and of a setting process in which solder paste areas Ea1, Ea2, Eb-Ed are extracted from image g4 and in which solder marks Em0 are set on the master printed circuit board Bf0.
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Inventors:
Kazuya Kotani
Application Number:
JP2011125811A
Publication Date:
November 25, 2015
Filing Date:
June 03, 2011
Export Citation:
Assignee:
Fuji Machine Manufacturing Co., Ltd.
International Classes:
H05K13/04; H05K13/08
Domestic Patent References:
| JP2008270696A | ||||
| JP2006108457A | ||||
| JP7120233A |
Attorney, Agent or Firm:
Tomoaki Higashiguchi
Shindo Motoko
Shindo Motoko