Title:
ELECTRONIC COMPONENT MOUNTING STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3920195
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method of an electronic component mounting structure in which an interlayer insulating film on a semiconductor chip is easily flattened in the electronic component mounting structure having a structure in which the semiconductor chip and the like are embedded in the interlayer insulating film on a base substrate.
SOLUTION: The method includes a process for forming a wiring pattern 28b in a part except for a mounting region on a body to be mounted 30a on which an electronic component 11 is mounted, a process for mounting the electronic component 11 on the mounting region of the body to be mounted 30a by turning a face where a connection terminal 12 is formed upward, and a process for forming an insulating film 30b covering the electronic component 11 and the wiring pattern 28b.
Inventors:
Masahiro Sunohara
Kei Murayama
Mitsutoshi Toko
Kei Murayama
Mitsutoshi Toko
Application Number:
JP2002327006A
Publication Date:
May 30, 2007
Filing Date:
November 11, 2002
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L23/12; H01L21/58; H01L21/68; H01L23/538; H05K1/18; H05K3/46; (IPC1-7): H01L23/12
Domestic Patent References:
| JP2000261152A | ||||
| JP2001007531A | ||||
| JP2001156457A | ||||
| JP5226387A | ||||
| JP2002226798A | ||||
| JP2001217387A |
Attorney, Agent or Firm:
Keizo Okamoto