Title:
ELECTRONIC INTEGRATED CIRCUIT PACKAGE
Document Type and Number:
Japanese Patent JP2950472
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a structure for facilitating edge mounting of a chip onto a board or another chip.
SOLUTION: The integrated circuit package derives enhanced mechanical rigidity and electrical reliability. Heat dissipation capacity is increased by bonding the edge of the integrated circuit chip 11 onto a board 16. Bonding is effected by forming a solder or a conductive adhesive between a bonding/ contact pad 15 on the board and a metallization structure extending at least into the limited facing region on the major surface of a chip. A thermal conductive material contained in a cap can impart an additional distributed support for the chip through combination of viscosity and density for imparting buoyancy of the chip.
Inventors:
MAAKU UINSENTO PIASON
SAASUTON BURAISU YANGUSU JUNIA
SAASUTON BURAISU YANGUSU JUNIA
Application Number:
JP545198A
Publication Date:
September 20, 1999
Filing Date:
January 14, 1998
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
H01L21/60; H01L23/367; H01L23/44; H01L23/473; H01L23/482; H01L25/00; H01L25/065; H01L25/07; H01L25/18; H05K7/20; (IPC1-7): H01L25/00
Domestic Patent References:
| JP6276753A | ||||
| JP3109351U |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)