Title:
符号化回路、復号回路、制御回路、記憶媒体および復号方法
Document Type and Number:
Japanese Patent JP7183479
Kind Code:
B2
Abstract:
An encoding circuit includes: a polar encoding unit capable of encoding a polar code of N bits; a frozen bit adding unit that generates a first sequence by adding frozen bits to an input signal; and a bit arrangement changing unit that: generates a second sequence of N bits by arranging the first sequence in the second sequence according to an arrangement rule dependent on a ratio of Nt bits, being a code length of a polar code to be encoded and being N bits or less, and N bits, and setting bit values at bit positions other than positions where the first sequence is arranged in the second sequence to zero when Nt bits are less than N bits; and inputs the second sequence to the polar encoding unit. A code word of Nt bits is generated by thinning processing based on a result of encoding the second sequence.
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Inventors:
Fujimori Takafumi
Application Number:
JP2022515960A
Publication Date:
December 05, 2022
Filing Date:
April 28, 2020
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03M13/13
Domestic Patent References:
| JP2018512784A |
Foreign References:
| US20170331590 | ||||
| US20190181983 |
Other References:
NTT DOCOMO,Discussion on construction of Polar codes,3GPP TSG RAN WG1 #88 R1-1702850,2017年02月17日,pp.1-9
Attorney, Agent or Firm:
Takamura Jun