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Title:
ENCRYPTION CIRCUIT AND DECRYPTION CIRCUIT
Document Type and Number:
Japanese Patent JP2009069686
Kind Code:
A
Abstract:

To provide an encryption circuit and a decryption circuit capable of, when data are initialized for each prescribed size to be encrypted or decrypted, reducing the burden of software processing for the initialization.

A CBC encryption circuit is constituted of an input register 11, a KEY register 12, an EXOR operation section 13, an AES encryption operation section 14, a selector 15, an IV register 16 holding an initial vector IV, and an output register 17. The CBC encryption circuit is also provided with: a counter 22 counting the number of times of encryption; a cycle register 23 wherein the number of times of encryption per cycle is set; and a comparison function section 24 which, when the first encryption is performed and when the counter value of the counter 22 and the number of times of encryption per cycle coincide, outputs an enable signal 35 and resets the counter 22. The selector 15 selects output of the initial vector IV when the enable signal 35 is input, and selects output of the AES encryption operation section 14 when the enable signal 35 is not input.


Inventors:
HERAI ATSUSHI
Application Number:
JP2007240076A
Publication Date:
April 02, 2009
Filing Date:
September 14, 2007
Export Citation:
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Assignee:
KONICA MINOLTA BUSINESS TECH
International Classes:
G09C1/00
Attorney, Agent or Firm:
Tomio Nagaishi