To provide an endian converter by which any trouble is not caused in the recognition of plural byte units without delaying an endian processing.

This endian converter is provided with a first switcher (1a), which accepts input byte data(DA1) consisting of plural type data and subjected to the first endian notation, a data size signal(DS) showing the number of bytes to be recognized as unit data, an endian switching signal(ES) for instructing the execution of endian conversion and a byte enable data(BE1) showing a byte position to be recognized as the unit data and subjected to the first endian notation, and outputs an output byte data(DA2) being the number of bytes shown by the data size signal(DS), maintaining the array of the byte position shown by the byte enable data(BE) and subjected to the second endian rotation when the endian switching signal(ES) shows the execution of the endian conversion.