Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ERRONEOUS ACTION DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5680895
Kind Code:
A
Abstract:

PURPOSE: To eliminate an erroneous action due to an error of the data and carry out a precise processing by starting the next data processing when a halfway data stored after the completion of CPU data processing coincide with a memory data in CPU.

CONSTITUTION: The data just before the amendment of the memory area M1 of the collect counting memory 6 is read and written in X register of the memory portion 11. Then, the content thereof is compared with the content of the data just before the amendment of a register 4, and when judging that they are not equal, the error display code is output from the memory portion 11. In this case, the processing action accompanying with the operation of the function key is not operated, small sum data of the memory area M2 is read out and written in X register. Then, when, judging the contents of X register and B register, if they are equal, they are written in the area M3. Similarly, when the content of X register is equal to that of the C register, the input practice processing by an operation of the function key is carried out. Then, in the case where one coincidence is present, the error is displayed.


Inventors:
YASUTAKE KUNIO
Application Number:
JP15582679A
Publication Date:
July 02, 1981
Filing Date:
November 30, 1979
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
CASIO COMPUTER CO LTD
International Classes:
G06F12/16; G11C29/00; (IPC1-7): G11C29/00