Title:
第１のクロックドメインと第２のクロックドメインとの間で伝送される主信号のためのエラーチェック
Document Type and Number:
Japanese Patent JP7420484
Kind Code:
B2
Abstract:
An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface (78) and a first redundant interface (80) in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface (82) and second redundant interface (84) in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry (87) is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.
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Inventors:
Saira Samar Malik
david joseph hawkins
andrew david toon
guanhui gen
Julian Jose Hilgenberg Pontes
david joseph hawkins
andrew david toon
guanhui gen
Julian Jose Hilgenberg Pontes
Application Number:
JP2019093466A
Publication Date:
January 23, 2024
Filing Date:
May 17, 2019
Export Citation:
Assignee:
Arm limited
International Classes:
G06F11/16; G06F13/38; H04L7/00
Foreign References:
| WO2016151674A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation Asamura Patent Office