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Patent Searching and Data


Title:
ERROR CORRECTION DEVICE IN MASK PATTERN DESIGN FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06110969
Kind Code:
A
Abstract:

PURPOSE: To eliminate correction omission and to reduce the number of times of geometric rule checking in the case of correcting the errors of mask pattern data at the time of designing mask pattern of an integrated circuit.

CONSTITUTION: By extracting error graphic coordinates from a checked result file at the time of correcting the errors for the mask pattern data (step A,) displaying the coordinates and the presence of correction on the screen of a computer (step B,) generating the command procedure of a mask pattern editor capable of easily performing the correction by the mask pattern editor by selecting the coordinates (step C) and performing the correction, the sure correction corresponding to the error coordinates can be performed.


Inventors:
ASO MASAO
Application Number:
JP25919392A
Publication Date:
April 22, 1994
Filing Date:
September 29, 1992
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G03F1/84; G06F17/50; (IPC1-7): G06F15/60; G03F1/08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)