To detect an error at a low cost for the circuit that is necessary for execution of a single 8-bit error detection system by detecting the error of the subject data or the initial parity data.

The error of the subject data or the retrieved initial parity data which are stored in a memory storage 110 is detected by the comparison of the initial parity data which are generated from the subject data received via an input line 102 by an ECC(error correction code) generator 104. Then the detected error is stored in the storage 110 for check of the parity data which are generated from the subject data retrieved out of the storage 110 by an ECC generator 116. If the initial parity data are not equal to the checked parity data, an error is decided. Then a signal showing the error is produced on an error correction state line 126.