PURPOSE: To facilitate the fault analysis by plural CPUs by writing a reset command and its factor in accordance with necessity in a log memory, in accordance with a fact that one of plural CPUs which have been connected to a common bus has issued the reset command.
CONSTITUTION: In accordance with a fact that for instance, a CPU (0) has issued (1) a reset command, a reset signal is set to, for instance, the CPU (0) system of a status register 3, and also, it is informed (3) to an MPU 5 by an NMI (nonmaskable interruption). Subsequently, the MPU 5 which has received this notice resets the circuit concerned [for instance, a circuit of the CPU (0) system] by the reset signal which has been read out of the status register 3, and also, writes a fat that this reset signal has been applied, in a log memory 6. In such a way, in accordance with a fact that one of plural CPUs which have been connected to a common bus issued the reset command, this reset command and its factor in accordance with necessity are written in the log memory 6, and can be collected as log information.
NISHIMURA NAOYUKI
HASHIMOTO SHIGERU
| JPS62285147A | 1987-12-11 | |||
| JPS537266A | 1978-01-23 |