To provide an error master detector that quickly detects bus error occurrence.

A bus permission signal synchronizing part 100 latches a bus permission signal generated when a bus master receives bus permission, a latch clock generating part 110 combines the bus permission signal and an output signal from the part 100 and generates a latch clock of bus master information, a 1st latching part 120 synchronizes with the latch clock, latches the precedent output signal and clears a latch value if a bus cycle normally finishes and a 2nd latching part 130 synchronizes with the latch clock and latches an output signal of the part 120. A master information selecting part 140 outputs the output signal of the part 120 if the bus master information that is latched by the part 130 does not exist, outputs the output signal of the part 130 if the bus master information exists and an error master storing part 150 stores an output signal of the part 140 when a bus error occurs.