PURPOSE: To shorten the stop time of a processor when an error occurs by duplexing an error information storage means which is controlled by means of a counter so as to provide it and switching it so as to use it.

CONSTITUTION: Switching circuits 30 and 31 are controlled by the least signifi cant bit of the couter 10 and a selection-side is inverted by permitting the count er 10 to be increased one by one. Thus, the roles of an error register 20 and an error register 21 are inverted. When error resetting is instructed, the content of the register 20 (21) which is not designated in the counter 10 is reset and the value of the counter 10 is increased one by one. Thus, error information is stored and only the resister 20 (21) which is not designated in the counter 10 is scanned out, whereby error information is set to be read.