Title:
ERROR SIGNAL INSULATION CIRCUIT
Document Type and Number:
Japanese Patent JP3303010
Kind Code:
B2
Abstract:
PURPOSE: To compensate for a loop for optimum stability and transition response by providing a pulse amplitude modulation means for selectively switching a shifted error voltage that passes through a twisted wire that is connected to an external supply voltage.
CONSTITUTION: A circuit has a peak current limitation, a self-oscillation PAM drive, a voltage-second equilibrium control, a shortage voltage lock-out, and a precise reference function. When a power is supplied from an external voltage 30, a drive voltage power supply Vcc is monitored by a pin 3 via resistance division consisting of resistors Ru and RL, and an internal reference voltage is applied to a non-inverted input of an error amplifier 10. Then, an output voltage is obtained at a pin 4, the difference between the error voltage and an ostensible fixed reference is amplified and is level-shifted to a pin 6 of a Vcc bus and is added to a buffer 50, and is used as the negative potential of a pulse amplitude modulation process, an at the same time the buffer 50 prevents a level-shift circuit 60 from being overloaded, thus compensating for a loop for optimum stability and transient response.
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| JPS5723206 | MAGNETIC SHIELDING MATERIAL |
Inventors:
Fernando Ramon Martin-Lopez
Richard Ledle
Richard Ledle
Application Number:
JP32601293A
Publication Date:
July 15, 2002
Filing Date:
November 30, 1993
Export Citation:
Assignee:
Toko Co., Ltd.
International Classes:
H01F27/36; H02M3/28; H02M3/335; H03K9/02; (IPC1-7): H02M3/28; H01F27/36
Domestic Patent References:
| JP1136563A | ||||
| JP447386U |
Attorney, Agent or Firm:
Nobuyuki Iida