Title:
ETCHING-BACK METHOD
Document Type and Number:
Japanese Patent JP3216207
Kind Code:
B2
Abstract:
PURPOSE: To lessen an interlayer insulating film in irregularities so as to improve a wiring layer formed on the interlayer insulating film in step coverage.
CONSTITUTION: The whole surface of an interlayer insulating film 12 is covered with a photoresist 13, the photoresist 13 is etched through a first-stage RIE to enable projections 12b of the interlayer insulating film 12 to be widely exposed out of the photoresist 13. Then, the photoresist 13 and the interlayer insulating film 12 are etched through a second-stage RIE under conditions that they are equal to each other in etching rate. Therefore, even if reaction products are generated from the interlayer insulating film 12, the photoresist 13 is locally affected by the reaction products, the affected region of the photoresist 13 is accelerated in etching rate, and a part of the interlayer insulating film 12 correspondent to the region concerned is quickly exposed, so that a recess is prevented from being formed on the interlayer insulating film 12 through an RIE carried out later.
Inventors:
Yoshitsugu Nishimoto
Application Number:
JP7847892A
Publication Date:
October 09, 2001
Filing Date:
February 28, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/302; H01L21/3065; H01L21/3205; (IPC1-7): H01L21/3065; H01L21/3205
Domestic Patent References:
| JP6323337A | ||||
| JP1212439A |
Attorney, Agent or Firm:
Masaru Tsuchiya