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Patent Searching and Data


Title:
EVALUATING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS63214677
Kind Code:
A
Abstract:

PURPOSE: To identify a latch-up occurrence place more accurately by applying a prescribed rectangular wave source voltage between the high-potential terminal and ground terminal of a semiconductor device to be evaluated and applying a prescribed trigger pulse corresponding to the on-off timing of the source voltage.

CONSTITUTION: The rectangular wave on-off source voltage (a) is applied between the high potential terminal 101 and ground terminal 103 of the semiconductor device 3 to be evaluated from a power source 1. The trigger pulse (b), on the other hand, is inputted from a trigger pulse power source 2. A latch-up state is caused at a point T2 of tie when the rectangular wave on-off source voltage is in an on-state and the trigger pulse is inputted from an input/output terminal 102. The state where the on-off source voltage is turned on, however, ends at a time interval T3, so the diffusion of heating value due to an overcurrent at the occurrence place of the latch-up state is suppressed and the latch-up occurrence place is identified more accurately eventually.


Inventors:
MURANAKA KIYOHIKO
Application Number:
JP4800487A
Publication Date:
September 07, 1988
Filing Date:
March 02, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/66; G01R31/26; H01L27/08; (IPC1-7): G01R31/26; H01L21/66; H01L27/08
Attorney, Agent or Firm:
Uchihara Shin