PURPOSE: To simply and accurately output the internal information of the evaluation chip even in the high-speed operation without increasing the number of package pins.

CONSTITUTION: The internal information outputted from a CPU part 110 to internal data buses DB0 to DB7 is latched by latch circuits 121 to 123 based on the latch signal to be outputted from the CPU part 110. In reading out the internal information, when the corresponding select signal SEL is inputted from the outside, an output select circuit 130 selects one output of the latch circuits 121 to 123 and outputs the output data from the internal data output terminal 143 to the outside through the latch data bus LDB0 to LDB7. The tracing or the like is performed for the output data.