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Title:
EVALUATION OF HUMIDITY RESISTANCE FOR HYBRID INTEGRATED CIRCUIT PACKAGE
Document Type and Number:
Japanese Patent JPS5912368
Kind Code:
A
Abstract:

PURPOSE: To evaluate the humidity resistance of a package by measuring an DC amplification factor of a transistor chip housed in a hybrid integrated circuit package.

CONSTITUTION: A transistor chip 2 is carried at an appropriate place on a pattern formed on a ceramic substrate 1 and a wiring 3 is done. Then, a packaging for evaluation is conducted with a molding resin 4. Thereafter, a module thus obtained is left alone in a constant humidity chamber of an appropriate atmosphere and taken out at an fixed time interval to measure hFE characteristic. Decision on the evaluation is done covering an actually used package and a package to be evaluated simultaneously by a relative comparison or on a different environmental condition. The acceptance or rejection is determined depending on the acceleration rate.


Inventors:
MIYAGI KIYOSHI
Application Number:
JP12165382A
Publication Date:
January 23, 1984
Filing Date:
July 13, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R27/02; H01L21/56; H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66; H01L23/02
Attorney, Agent or Firm:
Sadaichi Igita



 
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