EVALUATION METHOD FOR SEMICONDUCTOR DEVICE JUNCTION STRENGTH AND EVALUATION DEVICE AND SEMICONDUCTOR DEVICE

Japanese Patent JP3855741

B2

PROBLEM TO BE SOLVED: To provide an evaluation method for quantitatively conducting shock resistance evaluation in a junction of electronic components or electronic elements, selecting a suitable material so as not to damage reliability for a long time, and specifying a junction condition, and to provide an evaluation device.
SOLUTION: This junction strength evaluation method for a semiconductor device is that shock force is applied to the specified position of the semiconductor device, junction is broken, and energy required to breaking is defined as impact strength of the junction to use as the evaluation method for a semiconductor mounting part impact strength and its evaluation device. A jig conducting uniform motion is bumped against a solder ball mounting part of the semiconductor device as shock to broken the solder ball from the junction, energy required to breaking the junction of the solder ball is calculated from the variation of loads applied to the jig, and calculated value is defined as the impact strength in the junction of the solder ball mounting part to use as the evaluation method for the semiconductor mounting part impact strength and its evaluation device.

Toshiaki Morita
Ryoichi Kajiwara
Masahiro Koizumi
Kazuya Takahashi
Kazutoshi Ito
Kenichi Yamamoto
Asao Nishimura
Isao Ueno
Satoru Okabe

JP2001343990A

December 13, 2006

November 09, 2001

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株式会社日立製作所

G01N19/04; G01N3/31; H05K3/34; (IPC1-7): G01N19/04; G01N3/31; H05K3/34

JP2001025891A
JP2000321196A
JP11304680A
JP11153537A
JP8136429A
JP5312703A
JP5107147A
JP3146843A
JP60097237A

Manabu Inoue

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