Title:
EXCEPTION PROCESSOR
Document Type and Number:
Japanese Patent JP3229057
Kind Code:
B2
Abstract:
PURPOSE: To provide an exception processor capable of removing a specific exception processing time and a processing cycle to be required after operation, attaining high speed exception processing and simplying the control of an arithmetic processor.
CONSTITUTION: The exception processor is constituted of an exception forecasting circuit 100 for forecasting an exception to be generated as the computed result of a computing element 103 based upon inputted operand and operation instruction, an exception processing circuit 101 for executing processing to be executed when an exception is practically generated in parallel with the arithmetic processing of the computing element 103 based upon the forecasted result 6 of the circuit 100, an exception detecting circuit 102 for detecting an exception based upon the computed result 9 of the element 103, and a selector circuit 104 for selecting the processed result 7 of the circuit 101 as an operation result 11 when an exception is generated or selecting the processed result 10 of the element 103 as the result 11 when an exception is not practically generated based upon the result 8 of the circuit 102.
Inventors:
Nobuhiro Ide
Application Number:
JP3163193A
Publication Date:
November 12, 2001
Filing Date:
February 22, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F9/30; G06F7/00; G06F7/483; G06F7/499; G06F7/50; G06F7/52; G06F7/76; G06F9/305; G06F9/38; G06F9/46; G06F9/48; G06F11/00; (IPC1-7): G06F9/46; G06F7/00; G06F7/50; G06F7/52; G06F9/30; G06F9/305; G06F9/38; G06F11/00
Domestic Patent References:
| JP60142735A | ||||
| JP3278124A | ||||
| JP5224886A | ||||
| JP6337423A | ||||
| JP62151651U |
Other References:
吉田尊・他、「スーパースカラ向け高性能ＦＰＵの制御方式」、電子情報通信学会技術研究報告、Ｖｏｌ．９１、Ｎｏ．４９０（ＶＬＤ９１−１２８〜１４２）、社団法人電子情報通信学会・発行（１９９２年）、ｐｐ．１０５〜１１２（ＪＩＣＳＴ資料番号：Ｓ０５３２Ｂ）
福久浩人・他、「高性能スーパ・スカラプロセッサ用浮動小数点演算器」、電子情報通信学会技術研究報告、Ｖｏｌ．９２、Ｎｏ．２８９（ＣＰＳＹ９２−３４〜４４）、社団法人電子情報通信学会・発行（１９９２年）、ｐｐ．８１〜８８（特許庁ＣＳＤＢ文献番号：ＣＳＮＴ１９９９００５３３０１１）
鈴木一正・他、「ＡＬＵの例外処理の高速化手法」、電子情報通信学会技術研究報告、Ｖｏｌ．９２、Ｎｏ．２８９（ＣＰＳＹ９２−３４〜４４）、社団法人電子情報通信学会・発行（１９９２年）、ｐｐ．７３〜８０（特許庁ＣＳＤＢ文献番号：ＣＳＮＴ１９９９００５３３０１０）
福久浩人・他、「高性能スーパ・スカラプロセッサ用浮動小数点演算器」、電子情報通信学会技術研究報告、Ｖｏｌ．９２、Ｎｏ．２８９（ＣＰＳＹ９２−３４〜４４）、社団法人電子情報通信学会・発行（１９９２年）、ｐｐ．８１〜８８（特許庁ＣＳＤＢ文献番号：ＣＳＮＴ１９９９００５３３０１１）
鈴木一正・他、「ＡＬＵの例外処理の高速化手法」、電子情報通信学会技術研究報告、Ｖｏｌ．９２、Ｎｏ．２８９（ＣＰＳＹ９２−３４〜４４）、社団法人電子情報通信学会・発行（１９９２年）、ｐｐ．７３〜８０（特許庁ＣＳＤＢ文献番号：ＣＳＮＴ１９９９００５３３０１０）
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)
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